1. Field of the invention
The present invention relates to a semiconductor memory circuit, and more specifically to a semiconductor memory circuit configured so that information stored in a memory cell connected to a selected word line and a selected pair of digit lines is transferred to a sense amplifier through a switch circuit connected to the selected pair of digit lines, and through one or several stages of data bus lines for collecting information on a plurality of digit line pairs.
2. Description of related art
In conventional semiconductor memory circuits, each memory cell is connected to a pair of digit lines respectively pulled up by a pair of load transistors. The pair of digit lines are respectively connected through a pair of gate transistors to a pair of data bus lines, which are in turn connected to a sense amplifier and are also connected to a pair of driving transistors, respectively.
When a memory cell is selected, the pair of gate transistors connected to the digit line pair connected to the selected memory cell are turned on, and the pair of driving transistors connected to the data bus lines connected to the turned-on gate transistors are also turned on. In this condition, data is read out of the selected memory cell.
When data is read out of the memory cell, a data bus line potential, namely an input potential of the sense amplifier is determined by a conductivity ratio of the load transistors, the gate transistors, and the driving transistors. On the other hand, when the memory cell is in a non-selected condition, the corresponding gate transistors and the corresponding driving transistors are turned off, so that the data bus line potential is determined by auxiliary transistors which are provided for each of data bus line pair and which are ceaselessly maintained in an on condition. In other words, a standby current is flowed by these auxiliary transistors.
With this arrangement, data can be read out from a selected memory cell at a high speed by previously setting the data bus potential of the non-selection time at the same level as that of the selection time, by means of the auxiliary transistors. In an actual operation, however, off-timings of the gate transistors and the driving transistors after the reading of the memory cell has been completed are liable to deviate from each other. If the deviation of the off-timing between the gate transistors and the driving transistors becomes large, the data bus potential in a half-selected condition will transiently and rapidly change toward a voltage supply voltage. A a result, a long time becomes required for restoring an appropriate voltage after it becomes a complete non-selected condition, since a driving power of the permanent-on auxiliary transistors is small. On the other hand, if the data bus is selected in a condition in which the data bus potential of the non-selection time is greatly deviated from that of the selection time, a time for restoring the selection potential is required. As a result, a time required until it enters a normal sense amplifier operation will decrease an access speed.
In order to rapidly bring the potential of the non-selected data bus line to the set level, it is considered to increase a current driving capacity of the permanent-on auxiliary transistors. However, this is not preferable, since it results in increase of consumption power of the memory circuit.
In addition, since the circuit for setting the potential of the selected data bus and the circuit for setting the potential of the non-selected data bus are respectively formed of transistors having different shapes and powers, a difference between the selection time potential and the non-selection time potential is liable to occur due to variations in characteristics attributable to a manufacturing process.